1. Field of the Invention
The present invention relates to a device for distributing a signal from a signal source to a plurality of circuit units. In particular, the present invention relates to such a device, which is suited to distributing control signals, e.g. clock signals or command/address signals, in a memory system, to a plurality of memory chips arranged on the memory module.
2. Description of Prior Art
Generally, a memory module, for example a DRAM module, includes a plurality of memory chips, which are arranged on the board of the memory module, the latter normally referring to a multi-layer board. Further, a clock signal source is normally provided in the form of a PLL-chip (PLL=phase-locked loop). The phase-locked loop generates a clock signal, which is supplied to the memory chips.
Up until now, for ensuring synchronicity, the signal lines, on which the clock signal from the PLL was supplied to each memory chip, had to comprise the same electrical length. For realizing this objective, it has so far been necessary to provide a multitude of meandering structures on the memory module in order to implement the clock feed lines of varying lengths. To realize these meandering structures it is normally necessary to provide at least one additional layer on the board (PCB=printed circuit board), which, as a rule, involves a multi-layer board.